Let us understand in simple terms the memory access that is required for execution of an instruction from the main memory.  The data and the instructions are read from the main memory and then after the execution of the instruction is over they are written back onto the memory.  But what happens when the program in consideration is larger than the size of the available memory?  Virtual Memory is a concept that addresses this issue by allowing a program than is even larger than the size of the available free memory to be loaded and executed and eliminate the chances of external fragmentation.  Let us understand how this is accomplished.

The data and instructions of any process (a program in execution) or thread of execution within a process must be available to the CPU by residing in physical memory at the time of execution.  Virtual Memory refers to the concept in which a process of a larger size than available memory can be loaded and executed by loading the process in parts.  The Operating System maps the programmer's virtual addresses to real hardware storage addresses.  Mapping implies the correspondence between the virtual addresses and the physical addresses using virtual translation mechanisms as decided by the Operating System.  The program memory is divided into pages and the available physical memory into frames.  The page size is always equal to the frame size.  The page size is generally in a power of 2 to avoid the calculation involved to get the page number and the offset from the CPU generated address.

In the virtual memory systems, the addresses that the application programs deal with are known as virtual addresses.  These virtual addresses used by the application program are mapped to physical addresses by translation of these virtual addresses.  This is taken care of by the virtual memory system's address translation mechanism by mapping these virtual addresses to frame addresses using the Page Map Tables.  This is what we call the physical address in the main memory that can be used to refer to the contents from the memory.  The process address space implies the number of unique addresses needed to hold both the process and its data.   The virtual address space refers to the memory space of the virtual addresses.

The virtual address contains a page number and an offset.  This is mapped to the physical address by a technique of address resolution after searching the Page Map Table.  In order to maintain the accounting information of which pages are loaded into which frames, the Operating System maintains a Page Map Table.  This table contains the following:

·         The Page Number

·         The Offset

·         The Frame Number

·         The Reference Bit

·         The Presence Bit

·         The Dirty/Modified Bit

The Page Number refers to the number of the page in the virtual addressing mechanism for the page.  The offset indicates the relative address of a particular instruction in the page from the base of that page.  The frame number indicates the number of the physical frame in the memory that is divided into equal sized frames.  Note that the page size and the frame size are always equal so that a page can be easily mapped onto a frame in the main memory.  The reference bit indicates whether the page is being referenced.  The presence bit indicates whether the page is in memory.  The modified bit is set if the page has been modified after being loaded in memory.  The Page table is process specific and each process is allocated its own Page Table.  There is another table called the Page Table Register that contains the references to the Page Tables in memory.  Therefore, there is one Page Table Register for the entire system, but there can be multiple Page Map Tables, each belonging to a particular process.

In Virtual Memory systems, the Virtual Page Address Translation mechanism translates a virtual Page No to a Physical Frame No.  This translation is taken care of by a specific hardware called the Memory Management Unit (MMU) that is contained in the CPU.  The MMU is a hardware device responsible for handling memory accesses requests that come from the CPU.  Note that the addressing model in this case is defined by the CPU.  In order to facilitate faster page table lookups, the Operating System makes use of "Translation Look aside Buffers" (TLB) and ensures that the Page Tables are updated with each Page Fault.  A TLB is a buffer (or cache) in a CPU that contains parts of the page table of a particular process that translates the virtual address to a physical address.  Page Fault is discussed later in this article.